The nanometer era is over. On June 25, IBM announced the world's first sub-1 nanometer chip — a 0.7nm (7 angstrom) node with a completely new transistor architecture called nanostack. The chip packs nearly 100 billion transistorsonto a die the size of a fingernail, nearly double the density of IBM's 2nm chip from 2021.
Nanostack — Building Chips in Three Dimensions
The key innovation is nanostack— IBM's first 3D nanosheet-based transistor architecture. Instead of laying transistors flat on the silicon surface (the method used since the 1960s), nanostack vertically stacks and staggers transistors layer by layerusing wafer-to-wafer bonding. Each layer can use different materials optimized for its specific function — switching, power delivery, signal — rather than compromising on a single material stack for everything.
Researchers at IBM's Albany, NY facility validated the design through CMOS integration with ultra-thin dielectric bonding, functional inverter operation, and dual-channel engineering. A companion paper at VLSI 2026 showed 40% SRAM scaling using the same architecture — important for AI workloads that depend on high-bandwidth memory access.
Why this matters:The industry has been predicting the end of Moore's Law for decades. At sub-1nm, features approach the size of individual atoms — silicon atoms are about 0.2nm apart. IBM's roadmap projects at least another decade of scalingbeyond this node using nanostack.
The Production Path — 5 Years Out
IBM expects the earliest adoption of nanostack at the sub-1nm node with a path to production in as early as 5 years. Partners include ASML (High NA EUV lithography — the only tool capable of printing features this small), Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany facility will soon house a High NA EUV tool from ASML, essential for continued logic scaling.
IBM also announced Anderon— the world's first pure-play quantum foundry, a standalone company drawing on IBM's quantum computing and semiconductor expertise. The message is clear: IBM is positioning for the post-silicon era on two fronts — angstrom-scale classical chips and quantum wafers.
Sources: IBM Research, VLSI 2026 conference proceedings. Image: IBM chip under scanning electron microscope.